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Optimization of the maximum delay of global interconnects during layer assignment

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2 Author(s)
Saxena, P. ; Dept. of Comput. Sci., Illinois Univ., Champaign, IL, USA ; Liu, C.L.

Traditionally, interconnects in multilayer routing technologies have been routed greedily, one at a time. This yields good routings for the first few interconnect trees, but poor routings for the remaining trees. In contrast, we present a new performance-driven approach for layer assignment and routing in which the quality of the routing is largely order independent, minimizing the peak tree delays in the process. We introduce a dynamically adjusted area quota for each tree on each routing layer. This ensures that no tree uses up excessive routing space on the “good” layers. Since the parasitic coupling of different layers varies over a large range, assignment of the edges in the trees to specific routing layers has a large impact on the interconnect delay. Furthermore, we derive an expression for the contribution of an edge in a tree to the total delay of that tree as a function of the layer to which the edge is assigned. We use this expression to introduce a lookahead key for each edge of each tree that enables us to decide whether to route that edge immediately on the current layer or to postpone it to a subsequent layer. Our approach can be used to construct a performance-driven layer assignment and routing algorithm specifically tailored toward any given combination of the timing, routing and technology models. Our experimental results demonstrate that this approach consistently outperforms the multipass greedy scheme currently in vogue, both in worst case delay and in routability

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:20 ,  Issue: 4 )