Development of system-on-a-chip design methodology and products using flexible interconnect architecture approach

Improvement of the traditional ASIC design methodology is targeted towards achieving significant increase in design productivity. This is especially critical in handling complex system-on-a-chip (SOC) products that allow only a short design cycle. In order to meet delivery times and avoid loss of opportunity to market, a technique that allows reuse of pre-designed intellectual properties (IPs) must be developed. Designers at MIMOS' Microelectronics Lab focus on quick integration of CPU, peripherals and memory blocks to a flexible system interconnect architecture (IA) to aggressively shorten design time. This paper describes a versatile approach in IA-based SOC design and gives a detail accounts of integration of a variety of IPs to the IA.