By Topic

Development of system-on-a-chip design methodology and products using flexible interconnect architecture approach

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Yaakob, W.F.H. ; Microelectron. Lab., MIMOS Berhad, Kuala Lumpur, Malaysia ; Noor Beg, A.R.M. ; Rahman, A.A.A. ; Ahmad, M.R.

Improvement of the traditional ASIC design methodology is targeted towards achieving significant increase in design productivity. This is especially critical in handling complex system-on-a-chip (SOC) products that allow only a short design cycle. In order to meet delivery times and avoid loss of opportunity to market, a technique that allows reuse of pre-designed intellectual properties (IPs) must be developed. Designers at MIMOS' Microelectronics Lab focus on quick integration of CPU, peripherals and memory blocks to a flexible system interconnect architecture (IA) to aggressively shorten design time. This paper describes a versatile approach in IA-based SOC design and gives a detail accounts of integration of a variety of IPs to the IA

Published in:

Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on

Date of Conference: