A 10-bit, 20 Ms/s, 22 mW folding and interpolating CMOS ADC

This paper presents a 10 bit, low-power, 3.3 V folding and interpolating analog-to-digital converter (ADC). In this ADC, folder blocks with high folding factor are designed using a low-power, 3.3 V four-level folder to achieve the desired resolution. Also, the interpolation circuit and the current comparator are optimized for high accuracy and low-power consumption. The ADC is implemented in a 1.2 /spl mu/m CMOS technology, and measures 1.7 mm/spl times/1 mm (without pads). The results of HSPICE simulation with the level-39 MOSFET model illustrate a conversion rate of 20 Ms/s for a 2 MHz input signal, and a power dissipation of 22 mW from a single 3.3 V supply.