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Methodology of functional test synthesis and verification for VLSI systems

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1 Author(s)
Hudec, J. ; Fac. of Electr. Eng., Slovak Tech. Univ., Bratislava, Slovakia

This paper deals with a methodology for test synthesis and verification of VLSI and ASIC systems using an automatic functional test generator (AFTG). The proposed approach-the functional test generation methodology is based on specification and functional description of VLSI/ASIC systems. The determination of the test efficiency of instructions mixes is discussed.

Published in:

Information Technology Interfaces, 2000. ITI 2000. Proceedings of the 22nd International Conference on

Date of Conference:

16-16 June 2000

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