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Stochastic interconnect modeling, power trends, and performance characterization of 3-D circuits

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4 Author(s)
Rongtian Zhang ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Roy, K. ; Cheng-Kok Koh ; Janes, D.B.

Three-dimensional (3-D) technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. One of the purposes of realizing 3-D integration is to reduce the interconnect complexity and delay of two dimensions (2-D), which are widely considered as the barriers to continued performance gains in future technology generations. Thus, understanding the interconnect and its related issues, such as the impact on circuit performance, is key to 3-D circuit applications. In this paper, we present a stochastic 3-D interconnect model and study the impact of 3-D integration on circuit performance and power consumption. To model 3-D interconnect, we divide 3-D wires into two parts (horizontal wires and vertical wires) and derive their stochastic distributions. Based on those distributions, we estimate the delay distribution. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters, and dramatically improve circuit performance. With 3-D integration, circuits can be clocked at frequencies much higher (double or even triple) than 2-D

Published in:

Electron Devices, IEEE Transactions on  (Volume:48 ,  Issue: 4 )

Date of Publication:

Apr 2001

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