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A low-power asynchronous VLSI FIR filter

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2 Author(s)
Bartlett, V.A. ; Dept. of Electron. Syst., Westminster Univ., London, UK ; Grass, E.

An asynchronous FIR filter, based on a single bit-plane architecture with a data-dependent, dynamic-logic implementation, is presented. Its energy consumption and sample computation delay are shown to correlate approximately linearly with the total number of ones in its coefficient-set. The proposed architecture has the property that coefficients in a sign-magnitude representation can be handled at negligible overhead which, for typical filter coefficient-sets, is shown to offer significant benefits to both energy consumption and throughput. Transistor level simulations show energy consumption to be lower than in previously reported designs

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Advanced Research in VLSI, 2001. ARVLSI 2001. Proceedings. 2001 Conference on

Date of Conference: