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Limits of integrated-circuit manufacturing

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2 Author(s)
Doering, R. ; Texas Instrum. Inc., Dallas, TX, USA ; Nishi, Y.

A methodology is suggested for the study of integrated-circuit manufacturing limits. It is based on a hierarchical view of manufacturing detractors and associates limits with levels in this hierarchy. The methodology is illustrated with examples of steady-state, theoretical, and process limits at today's state of the art as well as example projections to future manufacturing at what may be near the limits of complementary metal-oxide-semiconductor (CMOS) scaling. There are also some speculations on possibilities beyond these limits

Published in:

Proceedings of the IEEE  (Volume:89 ,  Issue: 3 )

Date of Publication:

Mar 2001

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