By Topic

Power grid modeling technique for hierarchical power network analysis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)

This paper presents a novel power grid modeling technique that can be used in hierarchical power network analysis of multi-million gate designs. The RC network of the power grid of a macro block is extracted and reduced by an AWE-based algorithm. The resulting model replaces the macro blocks during the top level power network analysis, this greatly reduces both memory and CPU time usage. Our experiments show that more than 90% of R's and C's in the original power network can be reduced with less than 10% loss in accuracy. Furthermore, the CPU time required for the power network analysis of full-chip designs is reduced by 10 to 100 times

Published in:

Quality Electronic Design, 2001 International Symposium on

Date of Conference:

2001