Design of low-power high-speed maximum a priori decoder architectures

Future applications demand high-speed maximum a posteriori (MAP) decoders. In this paper, we present an in-depth study of design alternatives for high-speed MAP architectures with special emphasis on low power consumption. We exploit the inherent parallelism of the MAP algorithm to reduce power consumption on various abstraction levels. A fully parameterizable architecture is introduced which allows us to optimally adapt the architecture to the application requirements and the throughput. Intensive design space exploration has been carried out on a state-of-the-art 0.2 /spl mu/m technology, including efficient parallelism techniques, a data flow transformation for reduced power consumption, and an optimized FIFO implementation.