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Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding

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2 Author(s)
A. Chandra ; Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA ; K. Chakrabarty

We present a data compression method and decompression architecture for testing embedded cores in a system-on-a-chip (SOC). The proposed approach makes effective use of Golomb coding and the internal scan chains of the core under test, and provides significantly better results than a recent compression method that uses Golomb coding and a separate cyclical scan register (CSR). The use of the internal scan chain for decompression obviates the need for a CSR. In addition, the novel interleaving decompression architecture allows multiple cores in an SOC to be tested concurrently using a single ATE I/O channel. We demonstrate the effectiveness of the proposed approach by applying it to the ISCAS 89 benchmark circuits

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Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings

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