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Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

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2 Author(s)
Bainbridge, W.J. ; Dept. of Comput. Sci., Manchester Univ., UK ; Furber, S.B.

The demands of System-on-Chip (SoC) interconnect increasingly cannot be satisfied through the use of a shared bus. A common alternative, using unidirectional, point-to-point connections and multiplexers, results in much greater area requirements and still suffers from some of the same problems. This paper introduces a delay-insensitive, asynchronous approach to interconnect over long paths using 1-of-4 encoded channels switched through multiplexers. A reimplementation of the MARBLE SoC bus (as used in the AMULET3H chip) using this technique shows that it can provide a higher throughput than the simpler tristate bus while using a narrower datapath

Published in:

Asynchronus Circuits and Systems, 2001. ASYNC 2001. Seventh International Symposium on

Date of Conference:

2001