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CMOS circuit verification with symbolic switch-level timing simulation

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2 Author(s)
C. B. McDonald ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; R. E. Bryant

Symbolic switch-level simulation has been extensively applied to the functional verification of complementary metal-oxide-semiconductor (CMOS) circuitry. We have extended this technique to account for real-valued data-dependent delay values and have developed a novel mechanism for symbolically computing data-dependent Elmore delays. We present our symbolic simulation and delay calculation algorithms and discuss their application to the timing and functional verification of full-custom transistor-level CMOS circuitry

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:20 ,  Issue: 3 )