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A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell

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2 Author(s)
Perng-Fei Lin ; Nat. Taiwan Univ., Taipei, Taiwan ; Kuo, J.B.

This paper reports a 1-V 128-kb four-way set-associative CMOS cache memory implemented by a 0.18-μm CMOS technology using wordline-oriented tag-compare (WLOTC) structure with the 10-transistor tag cell usually for content-addressable memory (CAM) for low-voltage low-power VLSI system application. Owing to the WLOTC structure with the CAM 10-transistor tag cell for accommodating the one-step hit/miss generation and the dynamic pulse generators for realizing read-enable signals, a small hit access time (3.5 ns), low power consumption (4.1 mW at 50 MHz), and good expansion capability without sacrificing speed have been obtained

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:36 ,  Issue: 4 )