By Topic

Effectiveness of the ASIP design system PEAS-III in design of pipelined processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Kitajima, A. ; Dept. of Inf. & Math. Sci., Osaka Univ., Japan ; Itoh, M. ; Sato, J. ; Shiomi, A.
more authors

In this paper, the effectiveness of the ASIP (Application Specific Instruction set Processor) design system PEAS-III is evaluated through experiments. Examples in experiments are a MIPS R3000 compatible processor, DLX, a simple RISC controller, and PEAS-I core. While they are simple in-order pipelined processors, they have enough facilities for real embedded system design. Through experiments, easiness of design and modification for improvement and design quality in terms of performance and hardware cost are discussed. It has been confirmed that the design method used in PEAS-III is effective to design space exploration for simple pipelined processors

Published in:

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Date of Conference: