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Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

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3 Author(s)
Hosokawa, T. ; Corp. Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Tokyo, Japan ; Yoshimura, M. ; Ohta, M.

As an LSI is on the two-dimensional plane, the number of external pins of an LSI does not equally increase to the number of gates. Therefore, the number of flip-flops on a scan path is relatively increasing. As a result, the test application time becomes longer. In this paper, three new DFT strategies are proposed to reduce the test application time. Experimental results showed the DFT strategies reduced the test application times by 46 to 82% compared with a conventional full scan design method

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Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Date of Conference: