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Low-power high-level synthesis using latches

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3 Author(s)
Wooseung Yang ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea ; In-Cheol Park ; Chong-Min Kyung

High-level synthesis using latches has many merits in power, area and even in speed. But latches cannot be read and written at the same time and usually requires two-phase non-overlapping dock that is unpleasant choice for short-term design. In this paper we propose a storage allocation method that makes it possible to use latches as storage elements in single clocking scheme. The proposed method modifies the lifetime of variables slightly so that it can be applied to any high-level synthesis systems with small modification. The experimental results show 39-65% reduction in power consumption within almost the same area compared to the conventional power management scheme using clock gating

Published in:

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

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