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High-speed CMOS current-mode wave-pipelined analog-to-digital converter

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2 Author(s)
Chung-Yu Wu ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Yu-Yee Liow

In this paper, a new architecture 8-bit CMOS wave-pipelined current-mode A/D converter (IADC) is proposed and analyzed. The wave-pipelined theory is applied to the structure of the IADC. Thus, the conventional current sample-and-hold circuit is not needed in each stage of the pipelined IADC. From the HSPICE simulation results, the proposed IADC can achieve 8-bit accuracy with a sampling rate up to 20 MS/s when the input signal frequency is 900 kHz. The power dissipation of the IADC is 450 mW at 20 MS/s of conversion rate with a single 5 V power supply. The proposed IADC is designed and fabricated in a double-poly quadruple-metal 0.35 μm CMOS process

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Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on  (Volume:2 )

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