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The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor

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6 Author(s)
Xanthopoulos, T. ; Compaq Comput. Corp., Shrewsbury, MA, USA ; Bailey, D.W. ; Gangwar, A.K. ; Gowan, M.K.
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Single-wire, synchronous clocking systems for increasingly large and complex microprocessors present major technical challenges: Die size increases whereas target clock skew and jitter typically remain a constant percentage of a decreasing cycle time. The clocking methodology of the present Alpha microprocessor handles such challenges by radically departing from a single chip-wide clock distribution, to better control clock skew, jitter and power dissipation. Four major clocks (one reference and three derived) are used to clock separate chip sections.

Published in:

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Date of Conference:

7-7 Feb. 2001