By Topic

A low jitter 125-1250 MHz process independent 0.18 /spl mu/m CMOS PLL based on a sample-reset loop filter

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
6 Author(s)
Maxim, A. ; Crystal-Cirrus Logic Inc., Austin, TX, USA ; Scott, B. ; Schneider, E. ; Hagge, M.
more authors

This low-jitter high-resolution ripple-pole-less process-independent 0.18/spl mu/m CMOS PLL is based on a sample-reset loop filter technique. The key feature of this architecture is elimination of phase detector frequency spurs due to the ICO control current spikes during input phase difference. This is accomplished by averaging the charge injected by the proportional path over an entire input update period. As a consequence, the ICO control current has a shape characterized by a staircase of low amplitude steps, versus one characterized by narrow high amplitude pulses, and needs much less filtering for low-jitter operation.

Published in:

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Date of Conference:

7-7 Feb. 2001