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The advantage of rapid front-end design of an ASIC (implementation and verification of synthesizable RTL) can be easily lost during the back-end layout of a synthesized standard cell netlist. In deep submicron technologies, wire delay and area become the primary contributors to IC performance, power and area. The inaccuracy of wire modeling often leads to long physical and timing closure periods (achieving a placement which is routable and meets timing requirements) during floorplanning (FP) and place and route (P&R). A programmable DSP with 4 processing elements (PEs) connected to a split transaction bus is reported.