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More and more system-on-chip designs require the integration of analog circuits on large digital chips and therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on the analog circuits, information is needed about digital substrate noise generation. A methodology for modelling and simulating the time-domain waveform of the generated substrate noise of large digital circuits is verified with measurements on an 86k-gate CMOS ASIC. The difference between simulated and measured substrate noise RMS voltage is <10% and simulation time is of the same order of magnitude as a gate-level VHDL simulation. For smaller circuits, e.g., a 1k-gate multiplier, a speedup in simulation time of 3 orders of magnitude is obtained with respect to a full SPICE simulation.