Cart (Loading....) | Create Account
Close category search window

A 2.5 V 12 b 54 MSample/s 0.25 /spl mu/m CMOS ADC in 1 mm/sup 2/

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
5 Author(s)
Van Der Ploeg, H. ; Philips Res. Lab., Eindhoven, Netherlands ; Hoogzaad, G. ; Termeer, H.A.H. ; Vertregt, M.
more authors

Background digital offset extraction and analog compensation remove offset of the critical analog components. The calibrated two-step ADC achieves -70 dB THD in the Nyquist band with a 2.5 V supply. The ADC in 0.25 μm CMOS measures 1.0 mm/sup 2/ and dissipates 295 mW.

Published in:

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Date of Conference:

7-7 Feb. 2001

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.