By Topic

A 10 b 100 MSample/s CMOS pipelined ADC with 1.8 V power supply

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
4 Author(s)
Yong-In Park ; Texas Instrum. Inc., Dallas, TX, USA ; Karthikeyan, S. ; Tsay, F. ; Bartolome, E.

A 100 MHz ADC for low-power applications uses a 0.18 μm digital CMOS process. The design achieves 9.4 ENOB for a 50 MHz input at full sampling rate, and consumes a total of 180 mW with 2.5 mm/sup 2/ core in a single 1.8 V power supply.

Published in:

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Date of Conference:

7-7 Feb. 2001