A 10 b 100 MSample/s CMOS pipelined ADC with 1.8 V power supply

A 100 MHz ADC for low-power applications uses a 0.18 μm digital CMOS process. The design achieves 9.4 ENOB for a 50 MHz input at full sampling rate, and consumes a total of 180 mW with 2.5 mm/sup 2/ core in a single 1.8 V power supply.