An offset-cancelled CMOS clock-recovery/demux with a half-rate linear phase detector for 2.5 Gb/s optical communication

A 2.5 Gb/s optical receiver clock-recovery circuit in 0.25 /spl mu/m CMOS features 4 mV sensitivity and offset cancellation to enable an integrated limiting amplifier. A linear phase detector using a half-rate clock relaxes speed requirements. An active on-chip loop filter capacitor gives <0.1 dB jitter peaking.