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An offset-cancelled CMOS clock-recovery/demux with a half-rate linear phase detector for 2.5 Gb/s optical communication

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1 Author(s)
P. Larsson ; Lucent Technol. Bell Labs., Holmdel, NJ, USA

A 2.5 Gb/s optical receiver clock-recovery circuit in 0.25 /spl mu/m CMOS features 4 mV sensitivity and offset cancellation to enable an integrated limiting amplifier. A linear phase detector using a half-rate clock relaxes speed requirements. An active on-chip loop filter capacitor gives <0.1 dB jitter peaking.

Published in:

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Date of Conference:

7-7 Feb. 2001