Instruction scheduling for low power on dynamically variable voltage processors

Low power design has become an essential ingredient of modern VLSI design. In this paper, we consider low power design at the circuit and behavioral levels, and in particular, scheduling operations on dynamically variable voltage functional units. Previous attempts did not consider instruction latencies and pipelining effects in scheduling. We propose a timing-constrained and a resource-constrained instruction scheduling algorithm for low power on pipelined functional units considering instruction latencies. Experimental results from scheduling the operations of a digital lattice filter demonstrate the effectiveness of our algorithm