By Topic

Instruction scheduling for low power on dynamically variable voltage processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
M. M. Mansour ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; M. M. Mansour ; I. Hajj ; N. Shanbhag

Low power design has become an essential ingredient of modern VLSI design. In this paper, we consider low power design at the circuit and behavioral levels, and in particular, scheduling operations on dynamically variable voltage functional units. Previous attempts did not consider instruction latencies and pipelining effects in scheduling. We propose a timing-constrained and a resource-constrained instruction scheduling algorithm for low power on pipelined functional units considering instruction latencies. Experimental results from scheduling the operations of a digital lattice filter demonstrate the effectiveness of our algorithm

Published in:

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on  (Volume:1 )

Date of Conference: