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Area time power estimation for FPGA based designs at a behavioral level

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3 Author(s)
Bilavarn, S. ; Centre de Recherche, LESTER, Lorient, France ; Gogniat, G. ; Philippe, J.L.

A new performance estimation technique for FPGA implementation based designs is presented. The interest and originality of the method is to rapidly test a great number of implementation solutions while staying independent as far as possible of the technology used, and to include power consumption estimation. Thanks to this method, the designer can quickly have realistic information about the performances of a design, starting from a behavioral specification

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Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on  (Volume:1 )

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