By Topic

Area time power estimation for FPGA based designs at a behavioral level

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Bilavarn, S. ; Centre de Recherche, LESTER, Lorient, France ; Gogniat, G. ; Philippe, J.L.

A new performance estimation technique for FPGA implementation based designs is presented. The interest and originality of the method is to rapidly test a great number of implementation solutions while staying independent as far as possible of the technology used, and to include power consumption estimation. Thanks to this method, the designer can quickly have realistic information about the performances of a design, starting from a behavioral specification

Published in:

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on  (Volume:1 )

Date of Conference:

2000