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On efficient CPU-usage in a VLSI CAD-environment with application to circuit partitioning

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2 Author(s)
Wichlund, S. ; Nordic VLSI ASA, Tiller, Norway ; Aas, E.J.

We show experimentally that the number of clustering levels in a multilevel circuit partitioning algorithm may be reduced if guided by a measure of regularity applied to the input circuit netlist. Furthermore, we devise a simple tactic to reduce the number of runs in a multistart circuit partitioning algorithm. As a consequence CPU-time is saved. This comes at only a minor degradation in solution cost. Experiments were performed by applying our algorithm MLAF to the ISPD-98 benchmarks

Published in:
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on  (Volume:1 )

Date of Conference: 2000

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