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Efficient FPGA implementation of Gaussian noise generator for communication channel emulation

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4 Author(s)
Danger, J.-L. ; Ecole Nat. Superieure des Telecommun., Paris, France ; Ghazel, A. ; Boutillon, E. ; Laamari, H.

In this paper, a high accuracy Gaussian noise generator emulator is defined and optimized for hardware implementation on a FPGA. The proposed emulator is based on the Box-Muller method implemented by using ROM tabulation and a random memory access. By means of accumulations, the central limit method is applied to the Box-Muller output Gaussian distribution. After presenting the algorithmic method, this paper analyzes its efficiency for different noise signal formats. Then the architecture to fit into a FPGA is explained. Finally, results from the FPGA synthesis are given to show the value of this method for FPGA implementation

Published in:

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on  (Volume:1 )

Date of Conference:

2000