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Delay oriented design methodology: application to the design of a VHF low power VLSI polyphase oscillator

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4 Author(s)
A. Spataro ; Lab. IXL, Talence, France ; Y. Deval ; J. B. Begueret ; P. Fouillat

A new design methodology (Delay Oriented Design-DOD) has been developed in order to design a novel oscillator architecture. A 250 MHz DOD oscillator has been implemented on a 0.8 μm, two metal layers standard VLSI CMOS technology. It provides both in-phase and quadrature-phase differential outputs on a 60 MHz frequency range. The measured phase noise at 1 kHz offset from the carrier is about -92 dBc/Hz. The oscillator current consumption is 3 mA on a 3.3 V voltage supply

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Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on  (Volume:1 )

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