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A very-high-performance ultra-low-power signal processor chip-set has been developed for wideband adaptive radar and communications applications. The chip-set consists of a polyphase filter chip and a fast Fourier transform (FFT) chip. The chip-set performs polyphase channelization, which channelizes wideband digital data into multiple narrow subbands. The subsequent signal processing tasks such as adaptive beamforming, pulse compression, and space-time adaptive processing (STAP) are performed in the subband domain to mitigate dispersion effects. The power efficiency is achieved through highly optimized VLSI bit-level semi-systolic array technology. The chip-set was fabricated on a 0.25 micron bulk silicon CMOS process with the total two-chip die area of 1.6 square centimeters. The chip-set performs 54 billion arithmetic operations per second on 1.3 watts of power with 41 billion operations per second per watt power efficiency.