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5.5-V I/O in a 2.5-V 0.25-μm CMOS technology

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3 Author(s)
Annema, A.-J. ; Philips Res. Lab., Eindhoven, Netherlands ; Geelen, G.J.G.M. ; de Jong, P.C.

A robust high-voltage-tolerant I/O that does not need process options is presented, demonstrated on 5.5-V-tolerant I/O in a 2.5-V 0.25-μm CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation. Measurements on realized circuits, under accelerated stress conditions, indicate an extrapolated lifetime of hundreds of years for 5.5-V pad voltage swing, 2.2-V supply voltage. The shown concepts can easily be scaled toward newer processes or other interfacing voltages

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:36 ,  Issue: 3 )