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NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors

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10 Author(s)
Miwa, T. ; Syst. Devices & Fundamental Res., NEC Corp., Kanagawa, Japan ; Yamada, J. ; Koike, H. ; Toyoshima, H.
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This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A Vdd/2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies

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Solid-State Circuits, IEEE Journal of  (Volume:36 ,  Issue: 3 )