Referenced Items are not available for this document.
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns row-address-strobe access time and memory-cell area efficiency of 33% has been successfully developed with a single-side interface architecture, high-speed circuit design, and low-voltage design. In the high-speed circuit design, a multiword redundancy scheme and Y-select merged sense scheme are developed to achieve the performance goal. In the low-voltage design, a dual-complement charge-pump scheme and a decoupling capacitor utilizing a tantalum-oxide capacitor are developed to retain high performance at low supply voltage
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:36
,
Issue:
3
)
Date of Publication: Mar 2001
- Page(s):
- 503 - 509
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 6889735
- Digital Object Identifier :
- 10.1109/4.910489
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 07 August 2002
- Issue Date :
- Mar 2001
- Sponsored by :
- IEEE Solid-State Circuits Society
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