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A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

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2 Author(s)
S. B. Anand ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; B. Razavi

This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 27-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8×0.4 mm2

Published in:

IEEE Journal of Solid-State Circuits  (Volume:36 ,  Issue: 3 )