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We report a 72.8 GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350 mV logic swing at less than 0 dBm input power up to a maximum clock rate of 63 GHz and requires 86 dBm of input power at the minimum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1 V power supply. To our knowledge this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is also the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1 V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power delay product for a static divider operating above 30 GHz in any technology.
GaAs IC Symposium, 2000. 22nd Annual
Date of Conference: 5-8 Nov. 2000