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Converter-free multiple-voltage scaling techniques for low-power CMOS digital design

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3 Author(s)
Yi-Jong Yeh ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Sy-Yen Kuo ; Jing-Yang Jou

Recent research has shown that voltage scaling is a very effective technique for low-power design. This paper describes a voltage scaling technique to minimize the power consumption of a combinational circuit. First, the converter-free multiple-voltage (CFMV) structures are proposed, including the p-type, the n-type, and the two-way CFMV structures. The CFMV structures make use of multiple supply voltages and do not require level converters. In contrast, previous works employing multiple supply voltages need level converters to prevent static currents, which may result in large power consumption. In addition, the CFMV structures group the gates with the same supply voltage in a cluster to reduce the complexity of placement and routing for the subsequent physical layout stage. Next, we formulated the problem and proposed an efficient heuristic algorithm to solve it. The heuristic algorithm has been implemented in C and experiments were performed on the ISCAS85 circuits to demonstrate the effectiveness of our approach

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:20 ,  Issue: 1 )