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A smart memory architecture for the efficient support of artificial neural nets

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2 Author(s)
K. -E. Grosspietsch ; German Nat. Res. Center for Inf. Technol., St. Augustin, Germany ; J. Buddefeld

A “smart memory” approach is presented, i.e. the new architecture is achieved by extending the functionality of a conventional RAM structure. The architecture additionally contains two innovative features: To every word cell of w bits, a small q bits wide ALU is associated; and by means of extending the memory decoder, multiple access to certain sets of word cells within the memory as well as activation of their ALUs is possible. It is shown that based on these features, the standard numerical problem of adding up the m components of a vector of dimension m, in the new architecture can be carried out in a time complexity of O(square root(m)). For the execution of artificial neural nets, especially the on-line recognition of patterns mainly depends on the time-efficient efficient execution of weighted sums. It is shown that in our architecture, these weighted sums can be computed quite efficiently. The computation time is highly superior to the time complexity on sequential von Neumann machines. In addition, we show that if requested, the training mode of a neural net can also be significantly be speeded up. This is achieved by means of a simple crossbar switch which can be modularly added to the array of memory chips

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Parallel and Distributed Processing, 2001. Proceedings. Ninth Euromicro Workshop on

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