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This paper proposes a new yield management method for the SoC (System on a Chip) VYR (vertical yield ramp). In this method, test structures and analysis methods are adjusted to quantitatively analyze and optimize failure modes for improved yield. To verify the new methodology, two types of test chips were designed to monitor and distinguish the various failure modes affecting typical LSI product chips. It is concluded that the new methodology can diagnose and improve these several failure modes simultaneously to achieve the SoC VYR.