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RLC signal integrity analysis of high-speed global interconnects [CMOS]

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6 Author(s)
Xuejue Huang ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Yu Cao ; Sylvester, D. ; Shen Lin
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Inductive and capacitive coupling effects for high-speed global interconnects are studied via simulation. The impact of inductive coupling on delay and noise is found to be comparable to capacitive effects in high-speed buses. The results indicate that current-return paths are not strictly bounded by wide VDD/GND lines, so that inductive coupling is only partially eliminated by using shield wires. Shielding strategies for noise- and delay-sensitive nets is proposed, considering worst-case switching patterns.

Published in:

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Date of Conference:

10-13 Dec. 2000

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