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A high performance 0.25 um CMOS image sensor technology has been developed to overcome device scaling and process issues. Non-silicide source/drain pixel (3 transistors, 3.3 um/spl times/3.3 um, fill factor: 28%) is provided to reduce dark current and increase photoresponse. By optimizing thermal oxide in STI structure, double ion implanted source/drain junction and using H/sub 2/ annealing, the dark current can be drastically reduced (less than 0.5 fA per pixel). The color pixel performance with microlens and related crosstalk characters are also reported in this paper. Two photodiode structures are used to characterize pixel performance. The result shows NW/Psub photodiode demonstrate reduced dark current and higher sensitivity than N+PW diode.