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A 2.05 um/sup 2/ full CMOS ultra-low power SRAM cell with 0.15 nm generation single gate CMOS technology

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10 Author(s)
Jang, J.H. ; SRAM-1 Team, Samsung Electron. Co. Ltd., Yongin City, South Korea ; Kim, H.S. ; Baek, H.C. ; Na, J.J.
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We have developed a 2.05 um/sup 2/ full-CMOS ultra-low power SRAM Cell, which is probably the world-smallest, using 0.15 um generation single gate CMOS technology. The technology includes i) 0.15 um direct contact (to active region and gate poly) implemented by phase shift mask (PSM) and the shrinkage of contact by photo-resist (PR) reflow, ii) W-damascened local interconnection with 0.30 um pitch, iii) careful optimization of 0.17 um gate length buried channel (BC) pMOS to minimize the leakage current, while excludes self-aligned contact, Co-salicide, and rapid thermal annealing (RTA).

Published in:

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Date of Conference:

10-13 Dec. 2000