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The ultra-thin gate oxide required for the 0.13 /spl mu/m generation and beyond introduces a significant amount of gate-to-body tunneling current. The gate current modulates the body voltage and therefore the history effect. This paper discusses several methods to minimize the impact of gate current, which can cause excessive history effect in 0.10 /spl mu/m SOI CMOS. Our result demonstrates that the combination of high gate leakage and small junction capacitance can enhance circuit performance due to beneficial gate coupling. Ultra-low junction capacitance can be achieved by aggressive SOI thickness scaling, though, the proximity of source/drain extension and channel depletion to the buried oxide complicates device design and modeling.