By Topic

Controlling floating-body effects for 0.13 /spl mu/m and 0.10 /spl mu/m SOI CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

14 Author(s)
Fung, S.K.H. ; IBM SDRC, Hopewell Junction, NY, USA ; Zamdmer, N. ; Oldiges, P.J. ; Sleight, J.
more authors

The ultra-thin gate oxide required for the 0.13 /spl mu/m generation and beyond introduces a significant amount of gate-to-body tunneling current. The gate current modulates the body voltage and therefore the history effect. This paper discusses several methods to minimize the impact of gate current, which can cause excessive history effect in 0.10 /spl mu/m SOI CMOS. Our result demonstrates that the combination of high gate leakage and small junction capacitance can enhance circuit performance due to beneficial gate coupling. Ultra-low junction capacitance can be achieved by aggressive SOI thickness scaling, though, the proximity of source/drain extension and channel depletion to the buried oxide complicates device design and modeling.

Published in:

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Date of Conference:

10-13 Dec. 2000