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Hot carrier reliability for 0.13 /spl mu/m CMOS technology with dual gate oxide thickness

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9 Author(s)
Lin, C. ; Infineon Technol., Hopewell Junction, NY, USA ; Biesemans, S. ; Han, L.K. ; Houlihan, K.
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Different PMOS hot carrier degradation mechanisms are observed in a 0.13 /spl mu/m CMOS technology with ultra-thin gate oxide. Surprisingly, the gate voltage plays a significant role in total Idsat degradation, even at low temperature (40/spl deg/C). Hole trapping instead of electron trapping is observed under max Idsat degradation condition for PMOS. It is also shown that nitrogen affects NMOS and PMOS hot carrier degradation differently.

Published in:

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Date of Conference:

10-13 Dec. 2000