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Clock buffer circuit soft errors in antifuse-based field programmable gate arrays

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10 Author(s)
Jih-Jong Wang ; Actel Corp., Sunnyvale, CA, USA ; Katz, R.B. ; Dhaoui, F. ; McCollum, J.L.
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Three-dimensional mixed-mode device simulation is used to investigate the clock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned with improved SEU hardness. The threshold LET of each version was simulated both at static and during transition. Compared to the test data, the simulated results consistently underestimate the LETth. The difference between LETth at static and during transition is relatively small. This disagrees with the previous speculation that the clock upset is due to heavy-ion strikes very close to the clock edge. Efforts were also made to optimize the simulation methodology to reduce the simulation time for practicality

Published in:

Nuclear Science, IEEE Transactions on  (Volume:47 ,  Issue: 6 )

Date of Publication:

Dec 2000

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