Referenced Items are not available for this document.
A new cell design technique is described which may be used to create SEU hardened circuits. The technique uses actively biased, isolated well transistors to prevent transients in combinational logic from reaching the output node
Published in:
Nuclear Science, IEEE Transactions on
(Volume:47
,
Issue:
6
)
Date of Publication: Dec 2000
- Page(s):
- 2603 - 2608
- ISSN :
- 0018-9499
- INSPEC Accession Number:
- 6870137
- Digital Object Identifier :
- 10.1109/23.903815
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Dec 2000
- Sponsored by :
- IEEE Nuclear and Plasma Sciences Society
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