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Worst-case bias during total dose irradiation of SOI transistors

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9 Author(s)
V. Ferlet-Cavrois ; CEA, Centre d'Etudes de Bruyeres-le-Chatel, France ; T. Colladant ; P. Paillet ; J. L. Leray
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The worst case bias during total dose irradiation of partially depleted SOI transistors from two technologies is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide

Published in:

IEEE Transactions on Nuclear Science  (Volume:47 ,  Issue: 6 )