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Single-event upset and snapback in silicon-on-insulator devices and integrated circuits

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8 Author(s)
Dodd, P.E. ; Sandia Nat. Labs., Albuquerque, NM, USA ; Shaneyfelt, M.R. ; Walsh, D.S. ; Schwank, J.R.
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The characteristics of ion-induced charge collection and single-event upset are studied in silicon-on-insulator (SOI) transistors and circuits with various body tie structures. Impact ionization effects, including single-event snapback, are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMs, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMs is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed

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Nuclear Science, IEEE Transactions on  (Volume:47 ,  Issue: 6 )