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A digit pipelined dynamic time warp processor [word recognition]

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1 Author(s)
Irwin, M.J. ; Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA

A custom CMOS systolic design is presented which can achieve real-time isolated word recognition for large dictionaries. The design is based on the dynamic time warping (DTW) algorithm, an exhaustive search technique which permits nonlinear pattern matching between an unknown utterance and a reference word. This design differs from previous systolic DTW designs in that all data is represented in signed-digit, base-4 format, digits are passed between processing elements in a most-significant-digit-first, digit-serial fashion, and the algorithms are pipelined at the digit level. Using most-significant digit first data flow allows digit pipelining to succeed where conventional bit-serial pipelining has failed for the arithmetic operations required in the DTW algorithm. This allows a high degree of concurrency and a high data rate to be maintained, while the pin-out requirements are kept low. As many as 25 DTW processing elements will fit on one 128-pin chip. The VLSI DTW design presented is both flexible and modular. It is independent of the number of coefficients per frame and the precision of those coefficients. The design is easily expandable in the number of frames per word and the warp factor used to achieve the nonlinear matching

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Acoustics, Speech and Signal Processing, IEEE Transactions on  (Volume:36 ,  Issue: 9 )