By Topic

A new laser-processed polysilicon TFT architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Fulks, R.T. ; Electron. Mater. Lab., Xerox Palo Alto Res. Center, CA, USA ; Ho, J. ; Boyce, J.B.

A new top gate polysilicon thin-film transistor (TFT) architecture is introduced which requires only a single laser process step to simultaneously crystallize the channel and activate the source-drain. The dummy-gate TFT (DGTFT) uses a light blocking layer patterned with the gate mask combined with two backside expose steps to allow a self-aligned device structure. N-channel TFTs fabricated using the new process have field effect mobilities greater than 100 cm/sup 2//Vs. By controlling the backside exposures it is also possible to form offset or graded doping structures to reduce field enhanced leakage currents.

Published in:

Electron Device Letters, IEEE  (Volume:22 ,  Issue: 2 )