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Correlated double sampling integrator insensitive to parasitic capacitance

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3 Author(s)
Kajita, T. ; Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA ; Temes, G.C. ; Moon, U.-K.

A new correlated double sampling (CDS) scheme is proposed which improves the operation of an integrator with a large parasitic capacitor at the input node of an op-amp. It suppresses the effects of the 1/f noise and offset voltage of the op-amp, as well as the kTC charge noise from the parasitic capacitor. It also reduces charge injection and clock feedthrough effects

Published in:

Electronics Letters  (Volume:37 ,  Issue: 3 )